RTL Design

Systemverilog Design 3 : A Profession SoC RTL Code Walkthrough

Advance level course doing an end to end walk-through on a professional SoC in System

Lesson path

Modules and lessons

Each module keeps the academy sequence intact and opens available lessons directly on YouTube.

01Welcome1/1 lessons · 2m

02Interface1/1 lessons · 8m

2.1Writing InterfaceCourse: Systemverilog Design 3 : L2.1 : Writing Interface Definition8:38Watch

03Enumerations & Macros2/2 lessons · 6m

3.1Writing EnumerationCourse: Systemverilog Design 3 : L3.1 : Writing Enumerations4:10Watch
3.2Writing MacrosCourse: Systemverilog Design 3 : L3.2 : Writing Macros2:13Watch

04General Components5/5 lessons · 27m

4.1Writing General Components : ACourse: Systemverilog Design 3 : L4.1 : Writing General Components in RTL Design - Part A5:11Watch
4.2Writing General Components : BCourse: Systemverilog Design 3 :L4.2 : Writing General Components in RTL Design - Part B3:44Watch
4.3Writing General MacrosCourse: Systemverilog Design 3 : L4.3 : Writing General Macros in RTL Design with `define4:17Watch
4.4Writing FifoCourse: Systemverilog Design 3 : L4.4 : Writing Synthesizable FIFO in Systemverilog - Part A5:17Watch
4.5Writing Fifo ControlsCourse: Systemverilog Design 3 : L4.5 : Writing Synthesizable FIFO in Systemverilog - Part B9:27Watch

05DUT Spec3/3 lessons · 16m

5.1Axi & Ocp Protocol DescriptionCourse: Systemverilog Design 3 : L.5.1 : AXI & OPC Protocols Explained in Simplified Manner5:21Watch
5.2DUT FunctionalityCourse: Systemverilog Design 3 : L5.2 : Design Specification / DUT Functionality4:09Watch
5.3Axi Ocp ConvertorCourse: Systemverilog Design 3 : L5.3 : Description of AXI -OCP Protocol Convertor6:50Watch

06AXI to OCP Converter Code6/6 lessons · 53m

6.1AXI Write Front-End DescriptionCourse: Systemverilog Design 3 : L6.1 : AXI Write Front End Microarchitecture3:40Watch
6.2General Components CodeCourse: Systemverilog Design 3 : L6.2 : Writing Code for General Components4:15Watch
6.3AXI Write Front-End CodeCourse: Systemverilog Design 3 : L6.3 : Writing AXI Write Front-end FIFO Code14:26Watch
6.4AXI Read Front-End CodeCourse: Systemverilog Design 3 : L.64 : Writing AXI Read Front-end Code3:11Watch
6.5AXI-OCP State Machine DesignCourse: Systemverilog Design 3 : L6.5 : AXI - OCP State Machine Microarchitecture Details14:57Watch
6.6AXI-OCP Convertor CodeCourse: Systemverilog Design 3 : L.6.6 : Writing Code for AXI - OCP Converter12:59Watch

07OCP-AXI Convertor & Interconnect5/5 lessons · 28m

7.1OCP Read Return Front-EndCourse: Systemverilog Design 3 : L7.1 : Writing OCP Read-return Front-end6:56Watch
7.2OCP-AXI ConverterCourse: Systemverilog Design 3 : L7.2 : Writing OCP - AXI Converter8:40Watch
7.3Interconnect CodeCourse: Systemverilog Design 3 : L.7.3 : Writing DUT Top : Code for Interconnect Module4:15Watch
7.4SimulationCourse: Systemverilog Design 3 : L.7.4 : Simulation & Results6:13Watch
7.5Coding ConclusionCourse: Systemverilog Design 3 : L7.5 : Quick Rewind of the whole Code2:28Watch

08Summary1/1 lessons · 1m