RTL Design

Systemverilog Design 1 : Assignment Statements & Synthesis

Intermediate level course explaining assignment statements in SV & and their circuits generated in Synthesis

Lesson path

Modules and lessons

Each module keeps the academy sequence intact and opens available lessons directly on YouTube.

01Introduction1/1 lessons · 3m

02Latches Flipflops1/1 lessons · 1m

2.1Latches FlipflopsCourse: Systemverilog Design - 1 : L2.1: Latches Flip Flops1:13Watch

03Assignments Statements2/2 lessons · 3m

3.1Assignments SummaryCourse: Systemverilog Design - 1 : L3.1: Assignments in Verilog & SV2:28Watch
3.2Continuous & Procedural AssignmentsCourse: Systemverilog Design - 1 : L3.2 Continuous & Procedural Assignments in Systemverilog1:24Watch

04Always Statement in Verilog1/1 lessons · 4m

4.1Verilog Always BlockCourse: Systemverilog Design - 1 : L4.1 :Verilog Always Block4:43Watch

05Always statement in Systemverilog6/6 lessons · 10m

5.1'always' in SystemverilogCourse: Systemverilog Design - 1 : L5.1 : Always Block in Systemverilog0:55Watch
5.2'always_comb'Course: Systemverilog Design - 1 : L5.2 : always_comb in Systemverilog1:47Watch
5.3always_comb v/s always@(*)Course: Systemverilog Design - 1 : L5.3: always_comb vs always @(*) in Systemverilog1:55Watch
5.4'always_comb' ExampleCourse: Systemverilog Design - 1 : L5.4 : Example of using always_comb in Systemverilog2:16Watch
5.5'always_latch'Course: Systemverilog Design - 1 : L5.5 : always_latch in Systemverilog1:49Watch
5.6'always_ff'Course: Systemverilog Design - 1 : L5.6: always_ff in Systemverilog1:19Watch

06Blocking and Nonblocking Assignments5/5 lessons · 11m

6.1Blocking & Nonblocking AssignmentsCourse: Systemverilog Design - 1 : L6.1 : Blocking & Non Blocking Assignments in Systemverilog1:53Watch
6.2Blocking Assignment & Nonblocking Assignment in SimulationCourse: Systemverilog Design - 1 : L6.2 : Blocking & Non-Blocking Assignment Behaviour in Simulation3:38Watch
6.3Blocking Assignment & Nonblocking Assignment in SynthesisCourse: Systemverilog Design - 1 : L6.3 : Blocking & Non-Blocking Assignment Behaviour in Synthesis2:24Watch
6.4Blocking Assignment & Nonblocking Assignment in Synthesis ExampleCourse: Systemverilog Design - 1 : L6.4 : Blocking & Non-Blocking Assignment Synthesis Example2:31Watch
6.5Blocking Assignment & Nonblocking Assignment GuidelinesCourse: Systemverilog Design - 1 : L6.5 : Guidelines for Blocking Assignment vs NBA in RTL design1:12Watch

07Branching & Looping Statements4/4 lessons · 11m

7.1If StatementCourse: Systemverilog Design - 1 : L7.1 : Branching statements in Systemverilog RTL Design5:47Watch
7.2Case StatementCourse: Systemverilog Design - 1 : L7.2 : Using 'case' statement in RTL Design1:05Watch
7.3Looping StatementsCourse: Systemverilog Design - 1 : L7.3 : Looping statements usage in Systemverilog RTL Design Code2:28Watch
7.4Jumping StatementsCourse: Systemverilog Design - 1 : L7.4 : Jumping statements usage in Systemverilog RTL Design Code2:24Watch

08Summary1/1 lessons · 2m