RTL Design

Systemverilog Design 2 : Systemverilog Features for RTL Coding

Intermediate level course explaining SV specific features widely used for RTL design compared to Verilog

Lesson path

Modules and lessons

Each module keeps the academy sequence intact and opens available lessons directly on YouTube.

01Introduction1/1 lessons · 3m

02Constants & Parameters3/3 lessons · 5m

2.1Types of ConstantsCourse: Systemverilog Design - 2 : L2.1 : Types of Constants in Systemverilog2:24Watch
2.2Keyword ParameterCourse: Systemverilog Design - 2 : L2.2 : Using parameters in Systemverilog Design Coding1:18Watch
2.3Keyword Localparameter & ConstantsCourse: Systemverilog Design - 2 : L2.3 : Using localparam & const in Systemverilog RTL Design Code1:30Watch

03Parameterized Modules1/1 lessons · 3m

3.1Parameterized ModulesCourse: Systemverilog Design - 2 : L3.1: Parameterized Modules in Systemverilog3:20Watch

04Functions & Tasks4/4 lessons · 8m

4.1FunctionsCourse: Systemverilog Design - 2 : L4.1 : Functions in Systemverilog RTL Design Coding3:44Watch
4.2Verilog & Systemverilog FunctionsCourse: Systemverilog Design - 2 : L4.2: Comparing Verilog & Systemverilog Functions1:05Watch
4.3TaskCourse: Systemverilog Design - 2 : L4.3 : Using Task in Systemverilog1:52Watch
4.4Pass by ReferenceCourse: Systemverilog Design - 2 : L4.4 : Pass by reference in Systemverilog Functions1:31Watch

05Enumeration, Typedef & Structures3/3 lessons · 6m

5.1EnumerationCourse: Systemverilog Design - 2 : L5.1 : Using Enumeration in RTL Design Coding2:29Watch
5.2Type DefinitionCourse: Systemverilog Design - 2 : L5.2 : Using 'typedef' in RTL Coding in Systemverilog1:45Watch
5.3StructuresCourse: Systemverilog Design - 2 : L5.3 : Using Structures in RTL Design Coding1:57Watch

06Example : Structs & Enums3/3 lessons · 11m

6.1Example: SpecCourse: Systemverilog Design - 2 : L6.1: Simulation Example using struct & enum in SV: Specification2:56Watch
6.2Example: DesignCourse: Systemverilog Design - 2 : L6.2: Simulation Example using struct & enum in SV: Design Code2:38Watch
6.3Example:TestbenchCourse: Systemverilog Design - 2 : L6.3: Simulation Example using struct & enum in SV: TB Code5:50Watch

07Interfaces & Modports3/3 lessons · 8m

7.1InterfaceCourse: Systemverilog Design - 2 : L7.1 : Interfaces in RTL Design Coding3:36Watch
7.2ModportsCourse: Systemverilog Design - 2 : L7.2 : Modports in RTL Coding3:11Watch
7.3Connect Modules with/without InterfacesCourse: Systemverilog Design - 2 : L7.3 : Connecting Modules With & Without Using Interfaces in SV1:28Watch

08Generate Statements in Details5/5 lessons · 11m

8.1Generate StatementCourse: Systemverilog Design - 2 : L8.1 : Generate Statement in Systemverilog & Verilog0:52Watch
8.2Loop GenerateCourse: Systemverilog Design - 2 : L8.2 : Loop Generate Statements4:19Watch
8.3Conditional GenerateCourse: Systemverilog Design - 2 : L8.3 : Conditional Generate Statements1:44Watch
8.4Generate v/s AlwaysCourse: Systemverilog Design - 2 : L8.4 : Generate vs Always : What is the real difference & usage ?1:17Watch
8.5Example : Generate StatementCourse: Systemverilog Design - 2 : L8.5 : Simulation Example of Using Generate statement in RTL Code2:49Watch

09Summary1/1 lessons · 1m