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FREE Course: Systemverilog Essentials :
All you need to learn about SV to begin with.

Here is the complete course 'Systemverilog Essentials'  which is available for FREE, no sign-up needed !

You will learn the essentials of SV to start your career along with exercises. (Note that exercises are  not added to all lectures, they will be added  eventually).

Video Lecture
Exercise 
No exercise for this lecture
Click to see solution/ hints
2
Optional Lecture 1: VLSI in 30 minutes: IC Design & Manufacturing Overview
Video Lecture
Exercise 
No exercise for this lecture
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3
Optional Lecture 2: Graduate's Introduction to VLSI
Video Lecture
Exercise 
No exercise for this lecture
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4
Writing First Program (Module) in Systemverilog
Video Lecture
Exercise 
No exercise for this lecture

Write a simple 8 bit full adder in Systemverilog.

(For now, you can write it on a paper. )

 

From next module onwards, you need to write all programs and compile+simulate it. You can use the EDA playgrround to write+save+compile+simulate programs ,and in the next lecture, you will be seeing how to use EDA playground in more details.

Click to see solution/ hints

module adder (a,b,c_in,sum,c_out);

input logic [7:0] a;

input logic [7:0] b;

input logic c_in;

output logic [7:0] sum;

output logic c_out;

 

logic [8:0] result;

 

assign result=a+b+c_in;

assign sum=result[7:0];

assign c_out=result[8];

 

endmodule: adder

5
Writing First Test Bench Module in Systemverilog and Simulating for Free
Video Lecture
Exercise 
No exercise for this lecture

1. Write a simple 8 bit full adder in Systemverilog. Compile it and make it error free

 

2. Write a simple TestBench module for above adder module. You need to instantiate the DUT in the TB, connect DUT signals to TB local signals, drive few values into the inputs and verify the outpur by visual inspection.

 

 

From next module onwards, you need to write all programs and compile+simulate it. You can use the EDA playgrround to write+save+compile+simulate programs ,and in the next lecture, you will be seeing how to use EDA playground in more details.

Click to see solution/ hints

module testbench();

logic [7:0] tb_a;

logic [7:0] tb_b;

logic tb_c_in;

logic [7:0] tb_sum;

logic tb_c_out;

// Instantiaing the design module

adder adder1( .a(tb_a), .b(tb_b), .c_in(tb_c_in), .sum(tb_sum), .c_out(tb_c_out) );

// To dump signals to waveform

initial begin

$dumpfile("dump.vcd");

$dumpvars;

end

// Functional part of TB

initial begin

#1;

tb_a=1;

tb_b=2;

tb_c_in=1; // remove this and see

#1;

tb_a=10;

tb_b=25;

tb_c_in=1;

#1;

tb_a=30;

tb_b=40;

tb_c_in=1;

#1;

tb_a='hffff_ffff;

tb_b=1;

tb_c_in=1;

#1;

tb_a=0;

$finish();

end

endmodule: testbench

6
All about SV in 5 minutes
Video Lecture
Exercise 
No exercise for this lecture

There is no exercise to do for this leactue, but now you need to get the Systemverilog LRM (details below) . Go through the document quickly and see what all are there. You will be able to map the documnets to what you have seen in this lecture.

 

If you have access to IEEE from your university or company, get the latest document (2017) from IEEE as

 

https://ieeexplore.ieee.org/document/8299595

 

.Otherwise, get the 2012 LRM which is more than enough to learn almost anything in SV. You can search on google for "Systemverilog LRM" and still few universities gives the 2012 standand for free. (few links are below

 

http://www.ece.uah.edu/~gaede/cpe526/SystemVerilog_3.1a.pdf

)

 

Click to see solution/ hints

If you have access to IEEE from your university or company, get the latest document (2017) from IEEE as

https://ieeexplore.ieee.org/document/8299595

.Otherwise, get the 2012 LRM which is more than enough to learn almost anything in SV. You can search on google for "Systemverilog LRM" and still few universities gives the 2012 standand for free. (few links are below

http://www.ece.uah.edu/~gaede/cpe526/SystemVerilog_3.1a.pdf

)

7
SV Language Constructs Overview
Video Lecture
Exercise 
No exercise for this lecture
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8
Number Representation in SV
Video Lecture
Exercise 
No exercise for this lecture
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9
Systemverilog Datatypes
Video Lecture
Exercise 
No exercise for this lecture

dtq1

Click to see solution/ hints

dta1

10
Arrays in Systemverilog
Video Lecture
Exercise 
No exercise for this lecture
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11
Unpacked Arrays
Video Lecture
Exercise 
No exercise for this lecture
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12
Assignment Statements Overview
Video Lecture
Exercise 
No exercise for this lecture
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13
Blocking & Non-Blocking Assignments (NBA)
Video Lecture
Exercise 
No exercise for this lecture
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14
Conditional & Looping Statements
Video Lecture
Exercise 
No exercise for this lecture
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15
Functions & Tasks in Systemverilog
Video Lecture
Exercise 
No exercise for this lecture
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16
Sequential & Parallel Blocks in Systemverilog
Video Lecture
Exercise 
No exercise for this lecture
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17
Fork Join Types in SV
Video Lecture
Exercise 
No exercise for this lecture
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18
Semaphores
Video Lecture
Exercise 
No exercise for this lecture
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Video Lecture
Exercise 
No exercise for this lecture
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20
Events in Systemverilog
Video Lecture
Exercise 
No exercise for this lecture
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21
Clocking Blocks
Video Lecture
Exercise 
No exercise for this lecture
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22
Interfaces
Video Lecture
Exercise 
No exercise for this lecture
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23
Interfaces & Modports
Video Lecture
Exercise 
No exercise for this lecture
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25
Coding Example: Pure SV TB & Converting SV TB to Class based TB
Video Lecture
Exercise 
No exercise for this lecture
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26
Compiler Directives
Video Lecture
Exercise 
No exercise for this lecture
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27
Packages in Systemverilog
Video Lecture
Exercise 
No exercise for this lecture
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28
Parameters in Systemverilog
Video Lecture
Exercise 
No exercise for this lecture
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31
Additional Lecture 1: Enumerations in Systemverilog
Video Lecture
Exercise 
No exercise for this lecture
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32
Additional Lecture 2: Generate Statements
Video Lecture
Exercise 
No exercise for this lecture
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33
Additional Lecture 3: Systemverilog Time Regions Overview
Video Lecture
Exercise 
No exercise for this lecture
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